PWM Based Inverter using Spartan 6 FPGA

International Journal of Research and Scientific Innovation (IJRSI) | Volume V, Issue III, March 2018 | ISSN 2321–2705

PWM Based Inverter using Spartan 6 FPGA

Mahesh K. Patil1, Vinod B. Kumbhar2, Aditya N. Hambar3, Girish S. Hasure4

¹, ²Asst. Prof, Dept of Electronics, DKTES’s Textile & Engineering Institute, Ichalkaranji, Maharashtra, India
³Software Engineer, Global Edge Software Ltd, Bengaluru, Karnataka, India
⁴Project Engineer, Cerium Systems Pvt. Ltd, Bengaluru, Karnataka, India

Abstract–In this paper, two pulse width modulated outputs are produced using the Spartan 6 FPGA ANVYL board. The first output signal contains one pulse in 00 to 1800 and the second output signal contains same pulse as first output but shifted by 1800 i.e. in 1800 to 3600. The width these signal is changed using control inputs. This PWM output signal is used as control input to the inverter circuit. The power at the load connected to the inverter is observed by changing the widths of the PWM outputs.

Keywords- PWM, FPGA, ANVYL, ASIC

I. INTRODUCTION

Pulse width modulation techniques have been intensively researched in the past few years. Methods, of various concept and performance, have been developed and described. Their design implementation depends on application type, power level, semiconductor devices used in the power converter, performance and cost criteria, all determining the PWM method. Two classes of PWM techniques have been identified: optimal PWM and carrier PWM. The optimal PWM technique for producing switching pattern is based on the optimization of specific performance criteria. In this case, the switching patterns are calculated a priorifor given operating conditions and are then stored in memory (look-up tables) for use in real time. In this project two PWM outputs are generated. The first output signal contains one pulse in 0 to 180 degree and the second output signal will contain same pulse as first output but shifted by 180 degrees i.e. in 180 to 360 degree. The width of those can be changed using control inputs. FPGA is a Programmable Logic Device (PLD), comprising thousands of logic gates. Some of them are combined to form a configurable logic block (CLB). A CLB simplifies high-level circuit design. SRAM or ROM defines software interconnections between logic gates, providing flexible modification of the designed circuit, without altering the hardware. Concurrent operation, less hardware, easy and fast circuit modification, comparatively low cost for complex circuitry and rapid prototyping make it the favorite choice for prototyping an Application Specific Integrated Circuit (ASIC).

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