A Review: Bit Swapping Linear Feedback Shift Register for Low Power Dissipation

International Journal of Research and Scientific Innovation (IJRSI) | Volume V, Issue IV, April 2018 | ISSN 2321–2705

A Review: Bit Swapping Linear Feedback Shift Register for Low Power Dissipation

  Priyanka¹, Priyanka Bangari², Priyanka H G³, Rupesh N⁴, Praveen J⁵

 ^1-4UG student, ECE Department, Alva’s Institute of Engineering and Technology, Moodbidri, Karnataka, India
⁵Professor and Dean Academics, ECE Department, Alva’s Institute of Engineering and Technology, Moodbidri, Karnataka, India

Abstract- Bit swapping linear feedback shift register (BS-LFSR) is utilized in a conventional linear feedback shift register (LFSR) to decrease its power dissipation and enhance its performance. The proposed configuration, called bit-swapping LFSR (BS-LFSR), is made out of an LFSR and exclusive OR and a 2 × 1 multiplexer to decrease switching activity or number of transitions in bit swapping technique. Hence, it reduces dynamic power dissipation. Reduce in the dynamic power dissipation will decrease the efficiency of the circuit. Hence, the decrease in the switching activity will not decrease the performance.

Keywords-Bit Swapping Linear Feedback Shift Register, Built in Self-Test, Low

I. INTRODUCTION

The Bit Swapping Linear Feedback Shift Register (BSLFSR) is acquainted with upgrade the execution of the fundamental LFSR. The BS-LFSR configuration is principally concentrating on decreasing of power dissipation by decreasing the switching activity in a conventional LFSR without compromising its capacity and performance. Like a conventional LFSR, the BS-LFSR can likewise create pseudo-random values in the register because of the feedback component. BS-LFSR is typically utilized as a part of Built in Self-Test (BIST) as a test pattern generator (TPG) which requires producing a most sequence. BIST strategy permits an incorporated circuit (IC) to perform self-check and test without requiring any additional equipment. This will prompt a lessening in the cost for testing and maintenance of an IC by providing with the test machine. In addition, it can identify any IC disappointments in a short span interval.

The efficiency of the BS-LFSR depends not just on the parameters. There has been broad research did to expand the performance and area of very large scale integration (VLSI) plans and in this manner enhanced LFSR outline. In any ‘case, some of these works, however, give an optimized area and execution, experiences high power dissipation. Power dissipation is an essential thought in VLSI circuits as it is required to improve the battery dissipation and increment the reliability of the VLSI circuit. Subsequently, another plan concentrating on enhancing the power dissipation is especially required.

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