Photonic-Electronic Hybrid AI Accelerator for Next-Generation VLSI Systems

Authors

Jeyasudha S

PG Scholar, Dept. of M.E VLSI Design, Sree Sakthi Engineering College, Coimbatore, TN, India. (India)

Dr.P.Tamilselvi

Associate professor, Dept. of M.E VLSI Design, Sree Sakthi Engineering College, Coimbatore, TN, India. (India)

Article Information

DOI: 10.51244/IJRSI.2026.1309000056

Subject Category: Artificial Intelligence

Volume/Issue: 13/9 | Page No: 776-780

Publication Timeline

Submitted: 2026-09-18

Accepted: 2026-09-23

Published: 2026-10-05

Abstract

Artificial Intelligence (AI) applications such as deep learning, computer vision, natural language processing, and autonomous systems require high computational performance with minimal power consumption. Conventional CMOS-based AI accelerators are increasingly constrained by power dissipation, memory bottlenecks, and interconnect delays, limiting their scalability. This paper proposes a Photonic-Electronic Hybrid AI Accelerator for next-generation Very Large Scale Integration (VLSI) systems that combines the advantages of silicon photonics and CMOS electronics. In the proposed architecture, the photonic subsystem performs high-speed matrix multiplication using optical interference and wavelength division multiplexing, enabling massive parallel processing with ultra-low latency and reduced energy consumption. The electronic subsystem manages control logic, activation functions, memory access, and digital computations requiring high precision. The integrated design includes optical modulators, waveguides, photodetectors, CMOS controllers, SRAM buffers, and neural network processing elements on a single chip. Simulation results indicate improvements in throughput, computational efficiency, and power savings compared with conventional GPU- and TPU-based accelerators while maintaining high inference accuracy. The proposed accelerator is well suited for edge AI, autonomous vehicles, robotics, medical imaging, and cloud data centers where real-time processing and energy efficiency are essential. This hybrid architecture provides a scalable and practical solution for future AI hardware by leveraging photonic communication with advanced VLSI technology.

Keywords

Artificial Intelligence (AI), Photonic-Electronic Hybrid Accelerator, Silicon Photonics, VLSI Design, CMOS Technology,

Downloads

References

1. Shen, Y., Harris, N. C., Skirlo, S., et al., "Deep Learning with Coherent Nanophotonic Circuits," Nature Photonics, Vol. 11, No. 7, pp. 441–446, 2017. DOI: 10.1038/nphoton.2017.93. [Google Scholar] [Crossref]

2. Feldmann, J., Youngblood, N., Wright, C. D., Bhaskaran, H., & Pernice, W. H. P., "All-Optical Spiking Neurosynaptic Networks with Phase-Change Materials," Nature, Vol. 569, pp. 208–214, 2019. DOI: 10.1038/s41586-019-1157-8. [Google Scholar] [Crossref]

3. Xu, X., Tan, M., Corcoran, B., et al., "11 TOPS Photonic Convolutional Accelerator for Optical Neural Networks," Nature, Vol. 589, pp. 44–51, 2021. DOI: 10.1038/s41586-020-03070-1. [Google Scholar] [Crossref]

4. Tait, A. N., de Lima, T. F., Zhou, E., et al., "Neuromorphic Photonic Networks Using Silicon Photonic Weight Banks," IEEE Journal of Selected Topics in Quantum Electronics, Vol. 26, No. 1, Article No. 7700215, 2020. [Google Scholar] [Crossref]

5. Miscuglio, M., & Sorger, V. J., "Photonic Tensor Cores for Machine Learning," Applied Physics Reviews, Vol. 7, No. 3, Article 031404, 2020. [Google Scholar] [Crossref]

6. Rahim, A., Spuesens, T., Baets, R., & Bogaerts, W., "Open-Access Silicon Photonics: Current Status and Future Perspectives," IEEE Journal of Selected Topics in Quantum Electronics, Vol. 27, No. 2, Article No. 8200115, 2021. [Google Scholar] [Crossref]

7. Sun, C., Wade, M. T., Lee, Y., et al., "Single-Chip Microprocessor that Communicates Directly Using Light," Nature, Vol. 528, pp. 534–538, 2015. DOI: 10.1038/nature16454. [Google Scholar] [Crossref]

Metrics

Views & Downloads

Similar Articles