Photonic-Electronic Hybrid AI Accelerator for Next-Generation VLSI Systems
Authors
PG Scholar, Dept. of M.E VLSI Design, Sree Sakthi Engineering College, Coimbatore, TN, India. (India)
Associate professor, Dept. of M.E VLSI Design, Sree Sakthi Engineering College, Coimbatore, TN, India. (India)
Article Information
DOI: 10.51244/IJRSI.2026.1309000056
Subject Category: Artificial Intelligence
Volume/Issue: 13/9 | Page No: 776-780
Publication Timeline
Submitted: 2026-09-18
Accepted: 2026-09-23
Published: 2026-10-05
Abstract
Artificial Intelligence (AI) applications such as deep learning, computer vision, natural language processing, and autonomous systems require high computational performance with minimal power consumption. Conventional CMOS-based AI accelerators are increasingly constrained by power dissipation, memory bottlenecks, and interconnect delays, limiting their scalability. This paper proposes a Photonic-Electronic Hybrid AI Accelerator for next-generation Very Large Scale Integration (VLSI) systems that combines the advantages of silicon photonics and CMOS electronics. In the proposed architecture, the photonic subsystem performs high-speed matrix multiplication using optical interference and wavelength division multiplexing, enabling massive parallel processing with ultra-low latency and reduced energy consumption. The electronic subsystem manages control logic, activation functions, memory access, and digital computations requiring high precision. The integrated design includes optical modulators, waveguides, photodetectors, CMOS controllers, SRAM buffers, and neural network processing elements on a single chip. Simulation results indicate improvements in throughput, computational efficiency, and power savings compared with conventional GPU- and TPU-based accelerators while maintaining high inference accuracy. The proposed accelerator is well suited for edge AI, autonomous vehicles, robotics, medical imaging, and cloud data centers where real-time processing and energy efficiency are essential. This hybrid architecture provides a scalable and practical solution for future AI hardware by leveraging photonic communication with advanced VLSI technology.
Keywords
Artificial Intelligence (AI), Photonic-Electronic Hybrid Accelerator, Silicon Photonics, VLSI Design, CMOS Technology,
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References
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