Direct Memory Access Controller Design and Implementation for decreasing the Memory Access Time, Power and Area

International Journal of Research and Scientific Innovation (IJRSI) | Volume VI, Issue III, March 2019 | ISSN 2321–2705

Direct Memory Access Controller Design and Implementation for decreasing the Memory Access Time, Power and Area

Santosh Kumar B

CSE , New Horizon College of Engineering, Bengaluru, Karnataka, India

Abstract— Most of the newly developed stand alone embedded devices in the field of image, video and sound processing take more and more use of direct memory access controller. This controller is focused at high transmission capacity applications, for example, live video streaming. It is intended to drive 256-bit double data rate synchronous dynamic random access memory. The double data rate synchronous dynamic random access memory architecture utilizes a 2n-prefetch architecture, where the inner information transport is double the width of the outer information transport. A solitary read or compose cycle includes a solitary 2n-bit wide, one-clock-cycle information exchange at the center, and two relating n-bit wide, one-half-clock-cycle information exchanges at the I/O. Hence, this empowers fast activity as the inside section gets to are half the recurrence of the outer information exchange rate. Double data rate synchronous dynamic random access memories utilize a byte-wide, bidirectional information strobe that is transmitted remotely, alongside information (DQ) for information catch. Bidirectional information strobe is transmitted edge-adjusted by the double data rate synchronous dynamic random access memory amid peruses, and focus adjusted by the controller amid keeps in touch with the memory. The double data rate synchronous dynamic random access memory uses on-chip delay-bolted circles to check out bidirectional information strobe and comparing DQs, guaranteeing that they are very much coordinated and that they track each other with changes in voltage and temperature. For FPGA structure the IC producers are giving business memory controller IP centers working just on their items. Principle impediment is the absence of memory get to enhancement for arbitrary memory get to designs. The ‘data path’ some portion of those controllers can be utilized free of charge. This work propose a design of a double data rate synchronous dynamic random access memory controller, which exploits those accessible and well tested data paths and can be utilized for any reconfigurable device.

Keywords – Xilinx ISE, Direct Memory Access Controller, bidirectional information strobe.

I. INTRODUCTION

The extending execution hole among processors and memory has made the memory subsystem one of the restricting variables of a broadly useful PC framework’s execution. This marvel has been named the Memory Wall.

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