Test Architecture Optimization for 3-D Stacked ICS with Firm Dies
- August 17, 2018
- Posted by: RSIS
- Categories: Electrical and Electronics Engineering, Electronics & Communication Engineering
International Journal of Research and Scientific Innovation (IJRSI) | Volume V, Issue VIII, August 2018 | ISSN 2321–2705
Test Architecture Optimization for 3-D Stacked ICS with Firm Dies
Anoy Chowdhury
Brainware University, Kolkata, West Bengal, India
Abstract: The semiconductor industry is pushing relentlessly for high-performance and low-power chips. Recent advances in semiconductor manufacturing technology have enabled the creation of complete systems with direct stacking and bonding of die-on-die. These system chips are commonly referred to as 3-D stacked ICs (SICs). Through-silicon via (TSV)-based 3-D stacked ICs (SICs) are becoming increasingly important in the semiconductor industry. In this paper, we will try to address test architecture optimization for 3-D stacked ICs implemented using TSVs. We consider the case, namely 3-D SICs with firm die test architectures that are still need to be designed. Here we have to propose the solutions to achieve significant reduction in test length. This will be achieved through proposed test architecture and also to reduce the width of the Test Access Mechanism (TAM) by using serial/parallel conversion technique. Using TSV technology, 3-D ICs are created by placing multiple device layers together through wafer or die stacking, and these are then connected using vertical TSVs.
Keywords: 3-D stacked ICs, Through-silicon via (TSV), Test Access Mechanism (TAM)
I. INTRODUCTION
The semiconductor industry is pushing relentlessly for high-performance and low-power chips. Recent advances in semiconductor manufacturing technology have enabled the creation of complete systems with direct stacking and bonding of die-on-die. These system chips are commonly referred to as 3-D stacked ICs (SICs). Through-silicon via (TSV)-based 3-D stacked ICs (SICs) are becoming increasingly important in the semiconductor industry. In this paper, we will try to address test architecture optimization for 3-D stacked ICs implemented using TSVs. We consider the case, namely 3-D SICs with firm die test architectures that are still need to be designed. We next present the objective to derive optimal solutions for the architecture optimization problem for the above mentioned case.
