Design and Simulation of Modified ALU Based on QLUT

International Journal of Research and Scientific Innovation (IJRSI) | Volume V, Issue V, May 2018 | ISSN 2321–2705

Design and Simulation of Modified ALU Based on QLUT

Shreya V. Vaidya¹, Sheeja Suresh²

¹M.tech IV Sem (VLSI), G H Raisoni Institute of Engineering and Technology, Nagpur, Maharashtra, India
²Assistant professor (ETC), G H Raisoni Institute of Engineering and Technology, Nagpur, Maharashtra, India

Abstract: In today’s world where use of semiconductor technology is so wide area occupied by the circuit and delay are main points of concern. Interconnections are known to be main reason of the problem. With the use of multi valued logic (MVL). MVL is preferable our conventional binary logic as it gives optimum speed and better data handling capacity. In this paper we propose an ALU which is based on Quaternary logic look up table. Designed ALU is compatible with Standard CMOS technology. The Schematics are designed in S spice and simulation is done in T spice of the Tanner software.

Keywords: Multi valued logic (MVL), Arithmetic logic unit (ALU), Quaternary logic look up table, Tanner.

I. INTRODUCTION

ALU is important part of any processor. In this paper we propose a modified ALU which is based on Quaternary lookup table. MVL systems lead to saving in the number of interconnections. Due to the availability of the additional logic levels, the wires convey more information. It ultimately reduces the number of devices and leads to saving of area. Because of the use of quaternary lookup table instead of binary lookup table the power consumption and delay are reduced in this design. The transistor count is also reduced thereby reducing the area required. This design is compatible with standard CMOS. ALU is designed by mapping binary LUT into quaternary LUT with integrated circuits. Proposed ALU is implemented in Multiple-Valued voltage Mode Logic. The operands are converted to binary using a QtoB converter operations are performed in binary and results are converted to quaternary by using BtoQ decoder. This paper is organized as follows. In section II modules used to design the ALU are discussed in section III operator modules are with their simulation. In Section IV results and conclusion are given

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