Low power Canonical Signed Digit Multiplier using Spurious Power Suppression Technique Adder

International Journal of Research and Scientific Innovation (IJRSI) | Volume VI, Issue IV, April 2019 | ISSN 2321–2705

Low power Canonical Signed Digit Multiplier using Spurious Power Suppression Technique Adder

Sruthin Balachandran V V¹, Raghavendra Havaldar²

^1,2Assistant Professor, Department of Electronic and Communication, AJ Institute of Engineering and Technology, Mangaluru 575006, Karnataka, India

Abstract— The critical parameter to be considered in designing of integrated chips for smart handheld devices the power utilization in order to extend the battery lifetime so that device can be used for longer period. Due to the exponential growth in the development of wireless technology and in electronic devices- such as smart phones, smart TV etc- Digital signal processing applications have found to be used in these kinds of environments. But since DSP processing uses much complex algorithm for some applications, processing of it consumes more power. Hence low power consumption techniques are required for designing the DSP applications in Very large scale integrated circuits (VLSI). There are different techniques which are developed for reducing the power consumption, but have less effect in dynamic power consumption which governs the total power dissipation. This paper aims in designing a low power multiplier by making use of spurious power suppression technique (SPST). In this method, the arithmetic unit is separated into most significant part and least significant part, such that the MSP is switched off when it doesn’t affect the computation results, thereby reducing the dynamic power so that overall total power consumption of VLSI combinational circuit will be reduced. Also one more technique that is used in the proposed system that takes advantage of one of the characteristics is the Canonical signed digit recoding technique.
The proposed system is designed in Cadence software and the results obtained for 32 bit SPST adder shows significant reduction of 35.8% in power consumption and overall power consumption of proposed system is 0.561mW. Further the proposed system was used in power and area efficient 256 point FFT architecture, the results obtained showed reduction of 86.6% in power consumption.
This project can be implemented for real time application such as orthogonal frequency division multiplexing systems.

I. INTRODUCTION

The multiplier of DSP architecture plays a vital role in data processing. In every multiplier, the role of adders is to add the partial products obtained during multiplication process, and the number of adders depends on the number of partial products in a multiplier, which results in increased power consumption. As the technology is advancing, there is a requirement of multipliers with the reduced power consumption. Hence low power techniques are required to minimize the number of partial products and also to add the partial products efficiently.

Read More