Sobel Edge Detection Algorithm Using Verilog for 64 X 64 Grayscale Image

This paper presents the design and simulation of a Sobel edge detection module for 64×64 grayscale images using Verilog HDL. The architecture employs line buffers and a 3×3 convolution window to compute horizontal and vertical intensity gradients in a pipelined manner. Post-processing in Python is used to generate binary edge maps, intensity plots, and histograms for validation and visualization. The hardware pipeline achieves a throughput of one pixel per clock cycle after pipeline fill, requiring 4,096 cycles per frame. At a nominal 100 MHz clock, the design completes a frame in approximately 41 µs, corresponding to over 24,000 frames per second. Compared with a Python/OpenCV baseline, the Verilog implementation demonstrates an estimated 20–25× improvement in per-frame cycle efficiency. Although validated through simulation only, the design is synthesizable and provides a hardware-friendly framework for rapid prototyping of digital image processing algorithms.

Sobel operator, edge detection, Verilog HDL, FPGA simulation, image processing, Python visualization

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