International Journal of Research and Scientific Innovation (IJRSI) | Volume IV, Issue XII, December 2017 | ISSN 2321–2705

K. Madhuri[1], C.Bhargav[2], T.Chakrapani[3], K .Sudhakar[4]

[1]MTECH VLSI, Dept of ECE, ST.Johns College of Engineering and Technology, Kurnool, Andhra Pradesh, India.
[2]Assistant Professor, Dept of ECE, ST.Johns College of Engineering and Technology, Kurnool, Andhra Pradesh, India.
[3]Associate Professor, Dept of ECE, ST.Johns College of Engineering and Technology, Kurnool, Andhra Pradesh, India.
[4]H.O.D, Associate Professor, Dept of ECE, ST.Johns College of Engineering and Technology, Kurnool, Andhra Pradesh, India

Design of Low Power Binary Multiplier

Abstract: In today’s world of electronics industries low power has emerged as a principal theme. For integrated Chip, Power dissipation has become an important consideration as performance and area design. Due to increased complexity, reducing power consumption and over all power management of the IC are the key challenges. The need to reduce package cost and extended battery life is emphasis for many designs along with optimization of power and timing. Multipliers play a vital role in the computation part of ALU. Binary multiplication by digital circuits requires the generation of partial products, addition of partial product by reduction tree until two partial product rows remain and adding of partial product rows by an adder. In this project a low power binary multiplier is designed using voltage scaling technique.

Keywords: Multiplier, Power Dissipation, Voltage scaling, ALU

I. INTRODUCTION

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier. Thus making them suitable for various high speed, low power, and compact VLSI implementations. However area and speed are two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best trade off solution among the both of them. Generally as we know multiplication goes in two basic steps. Partial product and then addition. Hence in this project we have first tried to design different adders and compare their speed and complexity of circuit i.e. the area occupied. And then we have designed the Binary multiplier. II. MOTIVATION As the scale of integration keeps growing, more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amount of energy. While performance and Area remain to be the two major design tolls, power consumption has become a critical concern in today’s VLSI system design.

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