International Journal of Research and Scientific Innovation (IJRSI) | Volume IV, Issue XII, December 2017 | ISSN 2321–2705  

A Comparative Study of Power Dissipation of Sequential Circuits for 2N-2N2P, ECRL and PFAL Adiabatic Logic Families

Garima Madan
Assistant Professor, Department of Physics. Ram JaiPal College, Chapra, India

Abstract— Recent advances in compact, practical adiabatic computing circuits which demonstrate significant energy savings have renewed interest in using such techniques in low-power systems. In this paper power consumption of different sequential circuits like brute force latch , master slave D-flip flop and parallel-in-parallel-out shift registers based on different adiabatic logic families like 2N-2N2P, ECRL, PFAL were compared at 180 nm technology . Power consumption of PFAL adiabatic logic family is least in comparative to 2N-2N2P and ECRL adiabatic logic families. Maximum power consumption is obtained in ECRL family i.e. approximately 2.5 times greater than power consumption of 2N-2N2P logic family and 3.5 times greater than power consumption of PFAL logic family at various frequencies ranging from 350MHz to 500MHz.

Keywords- adiabatic logic design,master slave flip flop,low power sequential circuit,VLSI,shift registers.

I. INTRODUCTION

A limiting factor for the exponentially increasing integration of microelectronics is represented by the power dissipation. Though CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances, which cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses: the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused. In the literature, a multitude of adiabatic logic families are [1]-[11] .Each different implementation shows some particular advantages, but there are also some basic drawbacks for these circuits. The goal of this paper is to compare different adiabatic logic families by investigation of power dissipation and delays of some basic sequential circuits. For this purpose three adiabatic logic families 2N-2N2P, ECRL and PFAL are evaluated. The proposed circuits have been simulated and demonstrate adiabatic power savings over an operating frequency range from 350MHz to 500MHz at 180 nm technology.

A. Adiabatic switching

Adiabatic switching operation is an ideal condition, which may only be approached asymptotically as the switching process is slowed down.

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