Design and Analysis of 18 nm Graphene/TiO2/TiSix NMOS Device using Taguchi Method

Design and Analysis of 18 nm Graphene/TiO₂/TiSi_x NMOS Device using Taguchi Method

Muhammad Fawwaz Aqil Ahmad Fairuz¹, Afifah Maheran Abdul Hamid¹, Pritigavane Mogan¹, Nur Fathia ‘Azizi¹, Nur Hazwani Naili Mohd Nizam², Fauziyah Salehuddin¹, Khairil Ezwan Kaharudin³

¹Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Technology and Engineering Electronic and Computer (FTKEK), Universiti Teknikal Malaysia Melaka (UteM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia

^2,3Faculty of Technology and Applied Science, Innovative University College, Jalan SS7/26, 47301 Petaling Jaya, Selangor, Malaysia

DOI: https://dx.doi.org/10.47772/IJRISS.2025.909000720

Received: 26 September 2025; Accepted: 01 October 2025; Published: 28 October 2025

ABSTRACT

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been steady growth in high-speed switching applications in the semiconductor industry. The conventional combination of regular has to be replaced with high-k materials due to the limitation of shrinking the transistors. In this paper, Silicon Dioxide (SiO₂) and Polysilicon gate structure has been replaced with high-k materials and metal gate which are Titanium Dioxide (TiO₂) and Titanium Silicide (TiSi_x) respectively. The main objectives of this project are to reduce the leakage current (I_OFF) and optimum threshold voltage (V_TH) for the NMOS device. The designed and analyzed NMOS will be demonstrated in Silvaco software with ATHENA as a virtual fabrication process and ATLAS as analyzing the electric properties of the device. The results have been analyzed using Taguchi L9 orthogonal array method to obtain nominal values of threshold voltage and minimum value of leakage current. The initial results before optimizing with the Taguchi Method are 0.500061 V for V_TH and 13.2042 pA/μm for I_OFF. Once the device is optimized with Taguchi Method, the optimum value for V_TH is 0.540576 V and 12.9181 pA/μm for I_OFF. These values are met with the targeted values based on International Technology Roadmap for Semiconductors (ITRS) projection.

Keywords—NMOS, Taguchi, MOSFET, high-k

INTRODUCTION

In this study, an 18 nm NMOS device was designed through simulation as a virtual fabrication, featuring a gate structure composed of bilayer graphene, titanium dioxide (TiO₂) as the high-k gate dielectric, and titanium silicide (TiSiₓ) as the metal gate. The primary objectives were to optimize the threshold voltage (V_TH), minimize leakage current, and facilitate continued transistor scaling in line with ITRS projections. The proposed device demonstrates strong potential for fabrication with desirable electrical characteristics, highlighting the effectiveness of the selected materials and device architecture. Nevertheless, the integration of high-k materials presents several challenges, including threshold voltage instability and susceptibility to short-channel effects (SCEs), all of which necessitate careful process optimization [1].

V_TH is the most fundamental parameter that determines whether the transistor can operate correctly in ON/OFF states. Significant deviation of V_TH, particularly due to short-channel effects, directly threatens device functionality and circuit stability. In close relation, I_OFF represents the leakage current when the device is in the OFF state, and its value is strongly influenced by V_TH stability. A lowered or unstable V_TH often leads to an increase in I_OFF due to weakened electrostatic gate control (e.g., drain-induced barrier lowering), making both parameters inherently coupled and critical for ensuring low-power operation and robust short-channel suppression [2].

Moore’s Law predicts that the number of transistors in dense Integrated Circuits (ICs) doubles approximately every two years [3]. While this trend has driven rapid advancements in semiconductor technology, silicon dioxide-based gate dielectrics are approaching fundamental physical limits, leading to increased leakage currents and short-channel effects as devices scale down [4]. Consequently, researchers have identified graphene/high-k/metal gate structures as promising alternatives for next-generation CMOS technology, capable of overcoming the limitations of conventional silicon gates [5] [6].

High-k materials are favored because the relatively high bandgap and low dielectric constant of polysilicon limit its effectiveness in controlling gate electrostatics, particularly in nanoscale devices [7]. Polysilicon exhibits a relatively high bandgap and a low dielectric constant [8]. The incorporation of a metal gate not only enables precise threshold voltage control and reduces gate resistance, but also allows for the elimination of certain unnecessary implants, thereby improving device reliability and performance at scaled nodes [9].

Graphene has been explored as a gate/interfacial material that can actively influence threshold voltage and off-state leakage by tuning its work function and by forming heterojunctions with silicon; such approaches have demonstrated improved V_TH control and reduced I_OFF in several recent experimental and theoretical studies [10][11].

In addition to material selection, process optimization plays a crucial role in achieving desirable device characteristics. Ion implantation, for instance, can be adjusted to control junction depths and lateral dopant distributions, which directly influence threshold voltage (V_TH), subthreshold leakage, and short-channel behavior . By carefully tuning the ion dose and implantation parameters, it is possible to mitigate short-channel effects, suppress off-state leakage (I_OFF), and enhance the overall performance of NMOS devices [12]. Together, the integration of high-k/metal gate stacks and systematic process optimization provides a viable pathway for fabricating highly scaled transistors for future technology nodes, which can be utilized in the design and production of next-generation transistors.

In this study, an 18 nm NMOS device was designed through simulation as a virtual fabrication, featuring a gate structure composed of bilayer graphene, titanium dioxide (TiO₂) as the high-k gate dielectric, and titanium silicide (TiSiₓ) as the metal gate. The primary objectives were to optimize the threshold voltage (V_TH), minimize leakage current, and facilitate continued transistor scaling in line with ITRS projections. The proposed device demonstrates strong potential for fabrication with desirable electrical characteristics, highlighting the effectiveness of the selected materials and device architecture. Nevertheless, the integration of high-k materials presents several challenges, including threshold voltage instability, limited scaling potential, thermal reliability concerns, and susceptibility to short-channel effects (SCEs), all of which necessitate careful process optimization [1].

To address these challenges, the Taguchi method was employed in this study to systematically identify the critical process parameters influencing device performance. The Taguchi method enables optimization with fewer simulations while maintaining statistical robustness, thereby providing an efficient pathway to achieve the optimum electrical characteristics of the device [13].

METHODOLOGY

Fabrication Process (ATHENA)

Device construction was carried out using the ATHENA module, with High-k/Metal Gate (HKMG) technology applied during the fabrication process to realize the 18 nm metal gate. The design of the device involved specific adjustments tailored to the characteristics of the chosen materials and the device performance targets. Fig. 2 shows the fabrication process through the ATHENA simulation tools.

Fig. 1 18 nm NMOS Fabrication in ATHENA

Device Simulation (ATLAS)

Once the virtual fabrication of the device was completed, the 18 nm NMOS was simulated in ATLAS to extract its characteristics and electrical properties. As shown in Fig. 3, the process was carried out using ATLAS simulation tools.

Fig. 2 Device simulation 18nm NMOS in ATLAS

Taguchi Orthogonal L9 Array

In Table 1, four process parameters are identified for optimization through the Taguchi method, which applies about 36 experimental simulations incorporating two noise factors. [14]. Hence, as shown in Table I, Factor A represents Halo Implantation, Factor B represents Halo Tilt Angle, Factor C represents S/D Implantation, and Factor D represents Compensation Implantation. In addition, two noise factors were considered in the experiments: Factor X, corresponding to the Sacrificial Oxide Layer (PSG), and Factor Y, corresponding to the Oxide Temperature (BPSG), as listed in Table II.

Control Factors

Noise Factors

RESULTS AND DISCUSSION

Virtual Fabricated (ATHENA)

An 18 nm gate length is shown in the final structure of a planar NMOS device indicated as in Fig. 4.

Fig. 3 18nm NMOS device using Graphene/TiO₂/TiSi_x

Electrical Properties (ATLAS)

Fig. 5 and Fig. 6 show the electrical properties of the virtual fabricated 18 nm NMOS device designed in ATHENA.

Fig. 4 I_D-V_DS characteristic of the 18nm NMOS device

Fig. 5 I_D-V_GS characteristic of the 18nm NMOS device

Taguchi Method

The simulation results of the 36 experiments are shown in Table III and Table IV.

V_TH Results For Nmos Device

I_OFF Results For Nmos Device

The Smaller-the-Better (STB) and Nominal-the-Best (NTB) performance characteristics were employed in the S/N ratio analysis [15]. The NTB characteristic was applied for the V_TH analysis, whereas the STB characteristic was used for the I_OFF analysis. Two tables are showing the S/N ratio for V_TH and I_OFF, respectively (see Table V and Table VI).

S/N Ratio For V_TH

S/N Ratio For I_OFF

ANOVA was applied to evaluate the contribution of each factor affecting device performance, with the results shown in Tables VII and VIII.

ANOVA analysis for V_TH

Anova Analysis For I_OFF

In the factor analysis for V_TH, the Halo Tilt Angle was identified as the dominant factor, as it yielded the highest NTB factor effect. Conversely, S/D Implantation functioned more as an adjustment factor, showing a relatively low NTB value but a high Mean effect [16]. Hence, the S/D Implantation parameter was fine-tuned until the threshold voltage converged toward the nominal value projected by the ITRS. In the IOFF analysis, the Halo Tilt Angle again emerged as the dominant factor, contributing the highest factor effect of 10.98%. This dominance can be attributed to the Halo Tilt Angle’s strong influence on short-channel effects and junction profile control, which directly impacts leakage current behavior in scaled NMOS devices, as also reported by previous researchers [17][18].

The S/D implantation dose was then varied, until closely aligned with the ITRS projection. Based on the experiments, the optimal dose was determined to be 4.65×10¹³. Table IX presents the best-projected process parameter settings obtained from the Taguchi method. The final parameters were simulated with noise factors to obtain the optimum results, and a confirmation experiment with additional noise factors is summarized in Table X. After optimization, the best threshold voltage of the 18 nm NMOS device was recorded at 0.540576 V, which falls within the ITRS specification which is 0.540 V ± 12.7% [19].

Best Setting Simulation For V_TH

Confirmation Test Result For V_TH

For the leakage current (I_OFF) analysis, the optimal factor combination, corresponding to the highest STB values for each process parameter in Table VI was simulated, with the results summarized in Table XI. The lowest leakage current achieved was 12.9181 pA/μm, which is below the ITRS projected value, indicating an improvement in off-state device performance.

Finally, Table XIII presents the overall optimization results derived from the Taguchi method, together with a detailed comparison against the ITRS predictions to validate the effectiveness of the proposed process parameter tuning

Best Setting Simulation For I_OFF

Confirmation Test Result For I_OFF

Comparison V_th And I_off 18 nm Nmos Device

CONCLUSION

By first ensuring that V_TH and I_OFF are within an acceptable range, we establish the baseline stability of the device. If V_TH and I_OFF deviate too far from the target, further modeling or simulation may become irrelevant. Other analyses like example the mobility, gate capacitance, parasitics, temperature variation, process variation and interface behaviour will be addresses in future publications.

As a conclusions, an 18 nm NMOS device with a high-k/metal gate stack comprising bi-layer graphene, TiO₂, and TiSiₓ was successfully designed and optimized using Silvaco TCAD tools. The Taguchi L9 orthogonal array method was employed to systematically analyze the influence of process parameters on key electrical characteristics, namely threshold voltage (V_TH) and off-state leakage current (I_OFF). Factor analysis revealed that the Halo Tilt Angle was the dominant factor affecting both V_TH and I_OFF, while S/D Implantation acted as an adjustment parameter to fine-tune the threshold voltage toward the nominal value predicted by ITRS.

After optimization, the device achieved a threshold voltage of V_TH = 0.540576 V and a leakage current of I_OFF = 12.9181 pA/μm, both of which satisfy the ITRS projection. These results demonstrate that the application of the Taguchi method provides an effective approach for identifying critical process parameters and enhancing device performance. Overall, the findings confirm the potential of high-k/metal gate integration with advanced process optimization techniques for supporting further transistor scaling in future CMOS technologies.

ACKNOWLEDGMENT

The authors gratefully acknowledge the moral, operational, and financial support provided by the Micro & Nano Electronics (MiNE) Research Group, the Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronic and Computer Engineering (FTKEK), Universiti Teknikal Malaysia Melaka (UTeM), as well as the Ministry of Higher Education Malaysia (MoHE) throughout this research

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